This invention relates to dynamic thermal management, and particularly to dynamic thermal management in multi-dimensional integrated circuits or devices.
Three-dimensional (3D) integrated circuits (ICs) display clear advantages over their two-dimensional (2D) counterparts in terms of interconnect length, signal delay, packaging density, and noise immunity. However, their thermal characteristics are considered to be challenging. Recent research shows that multi-layer (or 3D) integrated circuits cause increased chip temperatures, yet the corresponding heating is within manageable limits. In general, thermal problems in 3D integration can be summarized as:                (i) Elevated lower density due to reduced footprint and surface area;        (ii) Increased distances from device layers to heat sink and heat spreader; and        (iii) Isolation of device layers through poor heat conductors (such as dielectrics, bonding materials, and alike).        
In the past years, as the ultra-large scale integration (ULSI) design became increasingly interconnect limited, three-dimensional integrated circuits gained significant interest. However, thermal management techniques specifically targeting three-dimensional integrated circuits need to be designed for these structures. Currently, there are no adequate techniques that exist for three-dimensional integrated circuits. Traditional temperature management techniques targeting the planar (two-dimensional) design philosophy are not capable of handling issues specific to the multi-layer characteristics of 3D ICs, such as, variation in distances to the heat sink and thermal interaction between device layers.
Therefore, it is desired to have techniques for temperature management in multi-dimensional integrated circuits or devices.